The present invention relates to a level conversion circuit for shifting the voltage level of an input signal to generate an output signal and to a semiconductor integrated circuit incorporating such a level conversion circuit.
An interface circuit that performs communication with a small amplitude signal, such as an emitter coupled logic (ECL), a stub series terminated logic (SSTL), or a low voltage differential signal (LVDS), is know in the prior art. In such an interface circuit, the small amplitude signal must be amplified to convert the small amplitude signal to a signal having a signal level that enables an internal circuit to function. An interface circuit normally includes a differential amplification circuit. In the differential amplification circuit, the circuit characteristics, such as delay time and output level, changes in accordance with the input level. Accordingly, there is a demand for a technique that minimizes fluctuation of the input level.
As one example, Japanese Patent No. 2773692 describes an input circuit that uses a differential amplification circuit. The input circuit functions as an interface circuit provided with a small amplification signal. FIG. 1 is a schematic circuit diagram of such an interface circuit 1.
As shown in FIG. 1, the interface circuit 1 includes a push-pull circuit 2 and a differential amplification circuit 3. The push-pull circuit 2 includes four MOS transistors M1 to M4. The MOS transistors M1 and M2 are connected in series between a first power supply having a high potential and a second power supply having a low potential. The MOS transistors M3 and M4 are also connected in series between the first and second power supplies. An input signal IN is provided to the gates of the MOS transistor M1 and M4. Reference voltage REF is supplied to the gates of the MOS transistors M2 and M3. The push-pull circuit 2 converts the input signal IN to two output signals OUT and OUTB. The output signal OUT is provided to the differential amplification circuit 3 from a node connecting the MOS transistors M1 and M2. The output signal OUTB is provided to the differential amplification circuit 3 from a node connecting the MOS transistors M3 and M4. The output signal OUT and the output signal OUTB are complementary to each other. The differential amplification circuit 3 amplifies the differential voltage between the two output signals OUT and OUTB provided from the push-pull circuit 2 to generate signal X.